dc.contributor.author | Shanker, Shreejith | |
dc.date.accessioned | 2022-11-13T12:40:40Z | |
dc.date.available | 2022-11-13T12:40:40Z | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022 | en |
dc.identifier.citation | Shashwat Khandelwal, Shanker Shreejith, A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN, International Conference on Field Programmable Technology, Hong Kong SAR, China, IEEE, 2022 | en |
dc.identifier.other | Y | |
dc.description.abstract | Recent years have seen an exponential rise in
complex software-driven functionality in vehicles, leading to
a rising number of electronic control units (ECUs), network
capabilities, and interfaces. These expanded capabilities also
bring-in new planes of vulnerabilities making intrusion detection
and management a critical capability; however, this can often
result in more ECUs and network elements due to the high
computational overheads. In this paper, we present a consolidated
ECU architecture incorporating an Intrusion Detection System
(IDS) for Automotive Controller Area Network (CAN) along
with traditional ECU functionality on an off-the-shelf hybrid
FPGA device, with near-zero overhead for the ECU functionality.
We propose two quantised multi-layer perceptrons (QMLP’s) as
isolated IDSs for detecting a range of attack vectors including
Denial-of-Service, Fuzzing and Spoofing, which are accelerated
using off-the-shelf deep-learning processing unit (DPU) IP block
from Xilinx, operating fully transparently to the software on
the ECU. The proposed models achieve the state-of-the-art
classification accuracy for all the attacks, while we observed a
15× reduction in power consumption when compared against
the GPU-based implementation of the same models quantised
using Nvidia libraries. We also achieved a 2.3× speed up in per-
message processing latency (at 0.24 ms from the arrival of a CAN
message) to meet the strict end-to-end latency on critical CAN
nodes and a 2.6× reduction in power consumption for inference
when compared to the state-of-the-art IDS models on embedded
IDS and loosely coupled IDS accelerators (GPUs) discussed in
the literature. | en |
dc.language.iso | en | en |
dc.publisher | IEEE | en |
dc.rights | Y | en |
dc.subject | Controller Area Network | en |
dc.subject | Intrusion Detection System | en |
dc.subject | Machine Learning | en |
dc.subject | Field Programmable Gate Arrays | en |
dc.title | A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN | en |
dc.title.alternative | International Conference on Field Programmable Technology | en |
dc.type | Conference Paper | en |
dc.type.supercollection | scholarly_publications | en |
dc.type.supercollection | refereed_publications | en |
dc.identifier.peoplefinderurl | http://people.tcd.ie/shankers | |
dc.identifier.rssinternalid | 247887 | |
dc.rights.ecaccessrights | openAccess | |
dc.subject.TCDTheme | Smart & Sustainable Planet | en |
dc.subject.TCDTheme | Telecommunications | en |
dc.subject.TCDTag | ARTIFICIAL NEURAL NETWORKS | en |
dc.subject.TCDTag | Artificial Intelligence | en |
dc.subject.TCDTag | Digital systems, representation | en |
dc.subject.TCDTag | Field Programmable Gate Arrays (FPGAs) | en |
dc.subject.TCDTag | Intelligent Vehicles | en |
dc.subject.TCDTag | NEURAL NETWORKS | en |
dc.subject.TCDTag | VHDL, FPGA, DIGITAL DESIGN | en |
dc.identifier.orcid_id | 0000-0002-9717-1804 | |
dc.identifier.uri | http://hdl.handle.net/2262/101547 | |