A scalable and reconfigurable shared memory architecture for large-scale graphics applications

Abstract

The computationally intensive nature of large-scale interactive graphics applications, such as photo-realistic rendering and low-latency virtual reality environments, has necessitated the use of parallel architectures in order to provide sufficient processing power to accommodate their demands. Scalable parallel architectures may be implemented using concurrent processing elements with attached local memory. In order to achieve interactive frame-rates, at high levels of detail, large quantities of information needs to be efficiently communicated between these concurrently operating processing elements as quickly as possible. This can be accomplished by utilising a distributed shared-memory architecture, incorporating a high-performance interface that is capable of attaining the required high-bandwidths and low-latencies. The integration of reconfigurable processing resources, in the form of field programmable gate arrays, into such a system allows the processing elements to be implemented directly in hardware, as close to the local memory as possible. This additionally allows for the hiding of access latencies to remote memory, through the use of local BlockRAM resources, in combination with a shared-memory abstraction. This fusion of local memory and reconfigurable logic resources, into a single global address space, allows for the implementation of efficient distributed algorithms in the logic of scalable parallel architectures that can be used to accelerate graphics applications. This thesis introduces a novel, low-cost, scalable, shared-memory architecture that was designed with the intention of accelerating graphics applications for large-scale interactive visualisations using a tightly coupled hybrid system of parallel commodity graphics and reconfigurable hardware resources. The custom-built nodes interface a single global address space that can be shared with a cluster of PCs. This shared address space is implemented through a dedicated, high-speed, low-latency commodity interconnect. Applications running across the cluster can benefit from increased performance by taking advantage of the parallel resources provided by the nodes and commodity PCs.