Nanofabrication and electronic transport properties of silicon nanowires

Abstract

This project develops a robust and reliable process to pattern sub 20 nm features in negative tone Hydrogen Silsesquioxane (HSQ) resist using high-resolution Electron Beam Lithography (EBL) and a low damage reactive ion etch (RIE) process to fabricate Silicon (Si) nanowires (NWs) on non-uniformly highly doped n-type Silicon-on-insulator (SOI) substrates. HSQ resist converts into Silicon dioxide due to its chemical composition on exposure under electron beam of high energy and become a very stable high resistance mask against RIE etching after further thermal treatment. In addition, it also acts as an insulating layer of few nanometers to avoid the shorting of the contact electrodes in a Hall structure used extensively in this investigation. Optimized processes for lithography, dry etch are employed to fabricate Hall bars 10 µm and 20 µm wide and NW devices with mean widths from 500 to 30 nm on SOI substrates having a device layer thickness of 45 nm and a doping density of ≈ 8×10 18 cm −3 at buried oxide to 5×10 19 cm −3 at the surface. The device layer of 45 nm in thickness. The devices are electrically characterized at room and cryogenic temperatures from 300 to 10 K to extract resistivity, mobility and carrier density for Si material as a film, microstructured Hall bar and nanowire. The room temperature mobility is observed to be 104 cm 2 /Vs for the Si film which is consistent with the literature for heavily doped Silicon having a doping level of 10 19 cm −3. For the Si Hall bar measurement, the obvious increase in mobility on reducing the size of the bar is observed, since the Hall contact electrodes are exactly opposite to each other which results in less error during the measurement. In addition, these contacts are made on the surface of the device layer where the doping level is high. Performing Hall measurements on single semiconductor NWs is a challenging task. To the best of our knowledge, only a few groups have been able to carry out these measurements so far [1-9]. For Silicon NWs from 30 to 500 nm, the Hall contacts of 200 nm in width are fabricated by using the nanowire as a shadow mask due to which the Hall contacts are not exactly opposite to each other. Thus, the Hall voltage signal is extracted from longitudinal electrodes. Both DC and AC measurements are performed on these Si Nanowires. Electron transport data in non-uniformly heavily doped silicon nanowires is extracted from these measurements. The DC Hall measurement of low mobility samples can result in a poor signal-to-noise ratio and suffer from additional problems such as enhanced electro-migration, thermal gradients, thermoelectric effects or Seebeck voltages whereas, the AC Hall effect measurement has demonstrated the ability to measure low mobility sample with greater resolution and reduced Joule heating and eliminates some slow thermal effects. So AC Hall effect measurements are employed to extract the transport behavior in narrow Si NWs. Two distinct options for AC measurement have been employed: 1) magnetic field sweeping in the range of ±14 T and 2) the sample is rotated under constant magnetic field at ±14 T. The second option is relatively economical as the cryostat ramping at high magnetic fields consumes a large amount of Helium per measurement. This approach minimizes the use of liquid Helium resources, while shortening substantially the acquisition time and therefore reducing the susceptibility towards thermal drift without compromising the accuracy of measurement. The Hall voltage of Si NWs are recorded from these measurements by using the Physical Property Measurement System (PPMS) controller software package for AC Magneto-Transport. This software, supersedes the standard PPMS MultiVu, allowing for extended device control and real-time data acquisition. For the pre-processes and fitting of the transport data, a custom routine written for Mathcad TM has been implemented, allowing for the asymmetric and symmetric with respect to field components of the pick-up to be extracted together with their magnitude and phase and as a function of field magnitude, angular orientation, and temperature. For 40 nm wide Si NW there is an increase in mobility 292 cm 2/Vs compared to other Si of larger width. This is due to the reduced dimensionality of electron transport in nanowires, caused by depletion effects. The depletion region formation results in reduced effective physical width of nanowires. The mean free path is theoretically calculated and directly compared with the widths of the nanowire, bar, and film by which it is approximated that the electron transport is 3 dimensional (3D) but is likely to be changed to quasi 1D transport respectively. Our device layer has a non-uniform dopant distribution profile, which is approximately one order of magnitude lower at the bottom of NWs. Given this situation, the depletion width along the height of Si NWs also varied depending on the position of the side wall contact. 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