CMOS power estimation

Abstract

The last decade has seen the inclusion of power consumption criteria in the list of design goals targeted by silicon designers and architects. Together with speed and area, low power is now a common part of a system specification. In tandem with this new technical challenge, market forces have driven electronic product development increasingly in the direction of portability. This consideration, in conjunction with a growing awareness of the environmental impact of increasing global energy consumption, has led to a substantial body of research devoted to minimising the energy consumption of electronic systems. This is a relatively new field of research within which there are many unexplored challenges, none more so than in the area of prediction of the likely operational power dissipation of the system. Such techniques must be capable of producing efficient, accurate estimates in the shortest possible time. It is the objective of this thesis to explore the problem of power estimation, with particular emphasis on processor systems. The focus of this work is on the input data sequence applied to the simulation model of the system.