Investigation of Copper/Graphene Composite Materials for Enhanced Electrical Conductivity Applications

Abstract

Copper plays a vital and ever-growing role in electrical power and signal transmission in the world today. This is due to its remarkable electrical properties, coupled with its low cost and abundance. In order to satisfy increasing demands on the performance of copper in such applications, the methods for improving the electrical conductivity of copper have become an area of extensive research. Given the limitations associated with purification and grain refining processes, the incorporation of nanoscale carbon structures into copper matrices as a means of producing composites with enhanced properties has emerged as a potential opportunity to meet future requirements. Within this category, the formation of copper/graphene composite materials has shown significant potential for producing copper structures with enhanced electrical conductivity.

However, the manufacture of such materials is supremely challenging, owing to the complexity of these composite architectures. This thesis aims to build on existing research conducted in this area by the experimental production of copper/graphene multi-layered composites with enhanced electrical conductivity.

Graphene was grown on the surfaces of micron scale copper foils by chemical vapour deposition (CVD). A novel CVD mounting system developed and used in this thesis enabled high-throughput production of these materials. These graphene-coated copper segments were stacked and consolidated by hot isostatic pressing to form copper/graphene muti-layered composites across a variety of different copper foil thicknesses. This yielded copper matrix composites with different graphene volume fractions ranging from 0.006-0.028 %. In addition to this, copper reference samples subjected to identical processing conditions, but without graphene growth, were used for reliable performance comparison. It was determined that the incorporation of graphene into the copper matrix systematically increased the composite conductivity with increased graphene loading level. An electrical conductivity ~21 % higher than the International Annealed Copper Standard was recorded in the composite with a graphene volume fraction of 0.028 % - the highest ever recorded for a copper/graphene composite.

The laminar architecture of the samples, coupled with the alteration to their mechanical properties by incorporation of graphene, gave rise to initial variations in the electrical response of the materials during testing with a standard four-point electrical probe technique, before saturating and flatlining. This is the first recorded incidence of these effects in copper/graphene composites.

Production of a nano-layered copper graphene composite with a graphene volume fraction of ~1.4 % was trialled, but the electrical data indicated that more sophisticated production and consolidation procedures will be required to generate these finer samples.

Derivation of the graphene sheet resistance in the composite with a graphene volume fraction of 0.028 % revealed that the sheet resistance of graphene in this composite was so low as to be unphysical (6.5x10-2 � sq-1) � contrasting with the prevailing mechanism of copper doping effects on graphene being the cause of the enhanced electrical conductivity. Computational studies have suggested that the stained geometry of copper in the copper/graphene composite increases the mean free path of copper at room temperature by inducing shifts in the phonon vibrational frequencies. As such, it is proposed that the graphene strain engineers the copper. Our preliminary microstructural investigations into potential strain effects in copper/graphene composites found that at higher graphene volume fractions, grain growth in copper appears to be supressed. This data forms a foundation for future analysis in this area.

The widespread availability of copper/graphene composites with enhanced electrical conductivity would have a huge impact on both large-scale electrical infrastructure and downscaled electronics. The work conducted in this thesis aims to promote further development in this field.