A study of electronic structure and thermal stability of engineered SOI material

Abstract

Silicon-on-insulator (SOI) consists of a thin Si layer known as the device layer, usually several tens of nanometres in thickness, bonded to a bulk Si wafer with an intermediate insulating oxide layer. While SOI is of potentially significant importance for the next generation of semiconductor processor technology, it is also interesting from a fundamental physics perspective. When the silicon device layer is very thin, the effective number of atoms contributing to its physical properties are finite and small compared to the bulk, and new electronic, mechanical and thermodynamic phenomena arise. The objective of this thesis is to provide new insights into the properties of silicon-on-oxide and the stability and electronic structure of patterned SOI. Any freshly formed silicon surface is highly reactive and in the presence of oxygen the surface immediately forms a thin layer of oxide known as a native oxide. Surface analysis of silicon samples by scanning tunneling microscopy (STM) – a key focus of this work – requires removal of the native oxide before measurement. Removing the thin native oxide layer from silicon in an ultra-high vacuum (UHV) environment involves annealing and processing SOI at elevated temperatures. The potential for modifying the chemical composition on the surface, the potential for contamination and loss of dopants, and potential loss of the structural integrity of the device layer are all major issues. In order to address this challenge, a low thermal budget process was developed. Following the refinement of the surface cleaning and preparation process, the capability of STM and scanning tunneling spectroscopy (STS) to study nanoscale Si(100) device layers in SOI was demonstrated. Specifically, how spreading resistance manifests in STM following the processing of SOI device layers with various doping levels have been analysed. It was also demonstrated that ultra-thin SOI with sufficiently high doping levels (~1020 cm-3) and device layer thicknesses down to 5 nm can be studied with STM and that these materials exhibit bulk like electronic characteristics. The evolution of the morphology of SOI due to annealing in an UHV environment was also investigated. In this work, preliminary measurements have suggested that SOI with thicknesses below 4 nm dewet spontaneously through a process that involves thermally driven fluctuations of the film thickness. Furthermore, measurements have showed evidence of the presence of an ultrathin wetting layer between the dewetting crystals of a 3 nm SOI film, consistent with the emergence of a new dewetting mechanism at these thicknesses. Finally, surface analysis of silicon nanowires of different widths, fabricated from SOI wafers using electron beam lithography was investigated. We have shown in this work that nanowires can be processed in UHV without affecting their structural integrity, using low thermal budget flashing and then analysed with STM. Furthermore, In order to carry out the surface analysis on smaller nanostructures beyond the limits of EBL, a simple nanowire and nanodisc fabrication technique has been developed.